1. Field of the Invention
Embodiments of the invention relate to the improvement of semiconductor device fabrication, more specifically to a method of improving mechanical integrity of a device by forming dielectric barrier films on a substrate
2. Description of the Related Art
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several years ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 90 nm feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
To further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (dielectric constant, k, of less than 4.0) to also reduce the capacitive coupling between adjacent metal lines. One such low k material is carbon doped silicon oxide that is deposited by a chemical vapor deposition process and may be used as a dielectric material in fabricating damascene features.
One conductive material having a low resistivity is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, a higher current, and higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern. Etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, for example, vias, and horizontal interconnects, for example, lines. Conductive materials, such as copper containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, is then removed.
Low dielectric constant (low k) films are used to improve interconnect RC delay, power dissipation, and crosstalk noise by reducing capacitance between interconnect metal lines. However, low k materials are often porous and susceptible to interlayer diffusion of conductive materials, such as copper, which can result in the formation of short-circuits and device failure. Dielectric barrier films are used to prevent copper diffusion into low k dielectric films and serve as an etch stop layer.
Several thermal curing methods have been established to further reduce the dielectric constant of deposited low k films. The methods for reducing the dielectric constants of the films should at least maintain or not degrade the physical properties of the films, while improving their electrical properties, such by reducing the presence of unwanted electrical charges within the material lattice and enhancing their performance as insulators. However, current thermal curing methods have proven unsatisfactory for curing films while retaining the desired physical properties of film stacks that include the low k films and barrier films as layers of the stacks.
Therefore, there remains a need for a method for depositing and curing dielectric layers while retaining the desired physical properties of film stacks that include the dielectric layers.